Enum varible as input and output port

SystemVerilog
,
1

I have package file which has only one typedef enum variable and I have import the package file in a module, used the enum variable as input and output port.



   package fsm_state;
      typedef enum {S1,S2,S3,S4} state_t;
   endpackage

   module fsm import fsm_state::*; (output state_t p1); endmodule  // working 

   module fsm import fsm_state::state_t; (output state_t p1); endmodule // getting error

if i import package as “import fsm_state::*” → it is working fine.

if i import only the variable “import fsm_state::state_t” → i’m getting error like “S1 is undefined”

what is the different between these two import ?

2

In reply to Malai_21:

On EDA Playground, your code works on all four simulators. Either your example isn’t representative of your issue, or you may have encountered a tool issue. Please contact your tool vendor for additional assistance.

3

In reply to cgales:

it a very long code, I have just mentioned a small part. it will be some thing similar to below code.


package fsm_state;
      typedef enum {S1,S2,S3,S4} state_t;
endpackage

module fsm import fsm_state::state_t; (
        input rstn, clk, start,
        output state_t state, next_state
    );
        always@ (posedge clk)
        begin
          if (!rstn) state <= S1;
            else state <= next_state;
        end
  
endmodule

i got same error in eda playground

Start time: 09:00:42 on Jun 24,2022
vlog -writetoplevels questa.tops -timescale 1ns/1ns design.sv testbench.sv
– Compiling package fsm_state
– Compiling module fsm
– Importing package fsm_state
** Error: testbench.sv(13): (vlog-2730) Undefined variable: ‘S1’.
End time: 09:00:42 on Jun 24,2022, Elapsed time: 0:00:00
Errors: 1, Warnings: 0

4

In reply to Malai_21:

Section 26.3 of the LRM discusses the import of enumerated types. The state_t is imported explicitly, but the enumerated literals are not.

As you discovered, using ‘import fsm_state::*’ will import all identifiers, or you can import the enumerated literals as needed with ‘import fsm_state::S1’