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  • enum type generation with distributed wight

enum type generation with distributed wight

SystemVerilog 4981
constraint dist 7
guy.levi
guy.levi
Forum Access
17 posts
September 07, 2017 at 2:02 pm

Hi all,

I have a constraint for an enum field in my packet class.

it is something like that

typedef enum {
	No_error,
        ERR1,
        ERR2,
        ..
        ..
        ERR20              	      
} Error_t;

I would like to have a distribution of lets say 25% "no_error" packets and all other options to be uniformly distributed.

my question is, is there a way to implicitly say "all other options" ?
something like -

constraint Error_Type_c {Error_Type dist {
No_error :=25,
??all other options ??:/75;}

I don't want to list explicitly all enum options (let say in the future I would extend the enum type and might forget to update the dist constraint and a value can be left out of generation)

thanks in advance ,
Guy

Replies

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dave_59
dave_59
Forum Moderator
8586 posts
September 08, 2017 at 7:38 am

In reply to guy.levi:

The best way to do this is to create a random error mode bit and put the distribution on that bit.

rand bit error mode;
rand Error_t Error_Type;
constraint Error_Type_c { error_mode dist {0:=25, 1:=75};
                          error_mode == 0 -> Error_Type == no_error;
                          solve error_mode before Error_Type;
                        }

— Dave Rich, Verification Architect, Siemens EDA

guy.levi
guy.levi
Forum Access
17 posts
September 08, 2017 at 11:30 am

In reply to dave_59:
thanks for your help Dave

Daniel Ciupitu
Daniel Ciupitu
Forum Access
1 post
September 14, 2017 at 8:52 am

Hi Guy,

Dave's solution is good but the percentage of no_error packets will be greater than 25%:

  • 25% because error_mode will be 0 in 25% of the cases
  • + an additional percentage because no_error will also appear when error_mode is 1

The complete solution is: 

  rand bit error_mode;
  rand Error_t Error_Type;
 
  constraint Error_Type_c {
    solve error_mode before Error_Type;
 
    error_mode dist {0:=25, 1:=75};
 
    error_mode == 0 -> Error_Type == no_error;
    error_mode == 1 -> Error_Type != no_error;
  }

Best regards,
Daniel.

guy.levi
guy.levi
Forum Access
17 posts
September 14, 2017 at 10:28 pm

In reply to ciupitudan:

oh, right.
Thanks for pointing this issue for me Daniel :)
10x,
Guy

Solution

Solution

Tudor Timi
Tudor Timi
Full Access
333 posts
September 27, 2017 at 8:38 am

You can also write dist constraints on expressions, which will make the code shorter:

constraint error_distribution { 
  Error_Type == No_error dist {
    0 := 25,
    1 := 75
  };

Constrained random thoughts on SystemVerilog and e: http://blog.verificationgentleman.com/

guy.levi
guy.levi
Forum Access
17 posts
September 27, 2017 at 1:13 pm

In reply to Tudor Timi:

very elegant : )

thanks!

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