Enum consisting of different data types

SystemVerilog
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Hi, Is it possible to make an enum consisting of different data types in System Verilog ?

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In reply to Ravi_Chandra:

An enum IS-A singular data type. Try explaining what your intended use is.

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In reply to dave_59:

In reply to Ravi_Chandra:
An enum IS-A singular data type. Try explaining what your intended use is.

There is no intended use. I was asked by another person regarding this. I was curious to know about the answer that question. I tried finding the answer from few of my friends by they too were not able to answer it. That’s all.

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In reply to Ravi_Chandra:

Then the direct answer to this is no. A enum specifies a restricted set of symbols/names with an integral type, each name having a unique value.