Endianness swap

SystemVerilog
,
1

Hello,

Is there any SV provided feature to swap endianness of a 256 bit variable?

for a 32bit example, the code is less:

assign data_swapped = {{data[07:00]},
{data[15:08]},
{data[23:16]},
{data[31:24]}};

but too much to type in (error prone) for 256 bit.

please advise.

Thanks

2

In reply to UVM_learner6:

assign data_swapped = {<<8{data}};

See section 11.4.14 Streaming operators (pack/unpack) in the IEEE 1800-2017 SystemVerilog LRM.

3

In reply to UVM_learner6:



module tb;
  
  initial begin
  
  int a = 'h12345678;
  int b;
    
    b = {<<byte {a}};
    
    $display ("A value is %h",a);
    $display ("B value is %h",b);
    
  end
endmodule
4

Hi ,

For 12345678 input ,the output is 78563412 not 87654321.

How to achieve 87654321.

Thanks

5

In reply to UVM_geek:

    b = {<<4 {a}};
6

Thank you Dave