Elegant way to define range of bits

SystemVerilog
,
1

Hi VA,

Looking for an elegant way I can define range of bits I am accessing in a vector, in some common place, which I can modify it and it will be waterfalled to all files in code using it, for example:
expected_txn.raw_data[rgb_pos-:5] = data_range_bus[28:24];
expected_txn.raw_data[rgb_pos+6-:6] = data_range_bus[17:12];

Will be happy if it could look like next:
… FIRST_RANGE 28:24
… SECOND_RANGE 17:12

expected_txn.raw_data[rgb_pos-:5] = data_range_bus[FIRST_RANGE];
expected_txn.raw_data[rgb_pos+6-:6] = data_range_bus[SECOND_RANGE];

Thanks,
Michael

2

In reply to Michael54:
May not be what you exactly want, but it’s a step in the right direction.


//xpected_txn.raw_data[rgb_pos-:5] = data_range_bus[28:24];
//expected_txn.raw_data[rgb_pos+6-:6] = data_range_bus[17:12];
module m;
  bit[31:0] v;
  let FIRST_RANGE =v[28:24];
  let SECOND_RANGE=v[17:12];
  
  initial begin
    FIRST_RANGE= 5'b11111;
    SECOND_RANGE=6'b110011;
    $display("v= %b", v);
  end
endmodule
// run 1ns
// # v= 00011111000000110011000000000000

    //expected_txn.raw_data[rgb_pos-:5] = data_range_bus[FIRST_RANGE];
    // expected_txn.raw_data[rgb_pos+6-:6] = data_range_bus[SECOND_RANGE];

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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3

In reply to ben@SystemVerilog.us:

Thanks Ben,
but it seems the “let” construct is tightly coupled with the variable “v”.
I am looking for this range declaration to be agnostic of the variable name…
Just to be a range:
28:24

4

In reply to Michael54:

Ben’s code was close.

package common_place;

  let FIRST_RANGE(v) = {v}[28:24];
  let SECOND_RANGE(v) = {v}[17:12];

endpackage 


import common_place::*;
...
expected_txn.raw_data[rgb_pos-:5] = FIRST_RANGE(data_range_bus);
expected_txn.raw_data[rgb_pos+6-:6] = SECOND_RANGE(data_range_bus);
5

In reply to dave_59:
Thank you Dave, you answered the question. My question though:
Do you really like this style? Isn’t it more confusing to have to do a lookup on the definition of the bits? An opinion…

6

In reply to ben@SystemVerilog.us:

There are other ways of addressing this:

  • packed unions
  • aliases
  • macros

It really depends on what the intended meanings of the ranges are.

7

In reply to dave_59:

In reply to ben@SystemVerilog.us:
There are other ways of addressing this:

  • packed unions
  • aliases
  • macros

It really depends on what the intended meanings of the ranges are.

Hi Dave,

First thanks for the suggestion with the “let” construct to be agnostic to variable name.

Could you please elaborate more on how packed unions, aliases or macros may address the bits ranges with agnostics to the variable?

Regards aliases in SV, read it is mainly used to connect nets/wires/ports in modules, please correct me if I am wrong?
So how can it be used in SV classes?

Thanks!
Michael

8

In reply to Michael54:

Knowing the full context of how you plan to use these ranges would help in getting better answers. I probably would not have mentioned the alias construct if you indicated this was for class based code in your original post, since that only works for renaming nets.

Using macros is probably the most straightforward approach and works almost anywhere

`define FIRST_RANGE 28:24
`define SECOND_RANGE 17:12
expected_txn.raw_data[rgb_pos-:5] = data_range_bus[`FIRST_RANGE];
expected_txn.raw_data[rgb_pos+6-:6] = data_range_bus[`SECOND_RANGE];

Using packed structs and unions is the elegant/structured way of doing this, but it requires that you declare the target variable using these types, or make and assignments through a temporary variable.

See some examples here and here.