Elaboration of exprssion (exp) [*0:$] intersect seq

SystemVerilog
1

Hi ,

could you provide how the through out operator is executed. (exp) [*0:$] intersect seq

i guess it is divided into two sequences one is (exp) [*0:] and the other one is seq. the sequence (exp) [*0:] is divided into (exp) or (exp ##1 exp) or …

after simulation of only (exp)[*1:$],I came to know that if exp is true in the current slot then repetition of expression is not checked from next clock on words. but from the through out operator meaning ,exp should hold true through out the sequence.is the meaning getting changed due to the context of through out operator.

and if we use (exp) [*1:] in the above sequence instead of (exp)[*0:] what would be the difference.

2

the sequence (exp) [*0:$] is divided into (exp) or (exp ##1 exp) or …

Wrong, the sequence (exp) [*0:$] is divided into

null or (exp) or (exp ##1 exp) or .....

A[*0] is null
A[*0] ##1 b // is same as
b

Ben systemverilog.us

3

In reply to ben@SystemVerilog.us:

Thanks ben for clarification.

in expression null or (exp) or (exp ##1 exp) or … intersect seq

the null doesn’t add any meaning as it is not of the form A[*0] ##1 b.

it seems (exp) [*0:] intersect seq , (exp) [*1:] intersect seq both are same. could you confirm .

I tried one example and find out both are same.

4

In reply to srbeeram:

it seems (exp) [*0:] intersect seq , (exp) [*1:] intersect seq both are same.

You’re correct. This is because something like:

a[*0:3] intersect b[*3] 
// IS SAME AS 
  (a[*0] or a[*1] or a[*2] or a[*3]) intersect b[*3]  // parentheses are needed 
// and in this case, because of the intersect, it is also the same as 
   a[*3] intersect b[*3]

One must be very cautious when using the [*0]; for example,

a and b[*0]   // is 0
a[*0] ##0 b // is 0 
a[*0] ##1 b // is same as (b)

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
5

In reply to ben@SystemVerilog.us:

Thanks Ben for clarifications.