Dynamic array default value in task/function

SystemVerilog
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1

Why is this piece of code giving me this warning in vopt:
“** Warning: … : (vopt-2737) ‘{ }’ may only be used with a queue.”

task automatic someTask1(
    input  some_enum_t       _a [] = '{},
    input  other_enum_t      _b [] = '{},
    input  bit               _c
  );

and this code is not giving the warning:

task automatic someTask2(
    input  some_enum_t       _a [] = {},
    input  other_enum_t      _b [] = {},
    input  bit               _c
  );

Isn’t the first one an array assignment pattern and the second concatenation?
So why is the first giving a warning?

I am using Questa 10.5. Both tasks are in a package.

What would be the proper way to set a dynamic array in a task/function to a default state of empty?
(so that the user doesn’t have to specify it if he doesn’t want to)

2

Your second code example is correct. The BNF does not allow for assignment patterns with an empty set of elements. You could also do
'{default:0}.

Earlier versions of SystemVerilog had some inconstantcies between assignment patterns and array concatenation involving queues that has since been cleaned up.

3

In reply to dave_59:

Hi Dave,

Thank you for the answer.

So when I want to set a dynamic array to an empty set of elements I use this syntax:

other_enum_t      _b [] = {}; // or other_enum_t      _b [] = '{default:0};

But, when I want to set a dynamic array to an non-empty set of elements I use this syntax:

other_enum_t      _b [] = '{ENUM1, ENUM2, ENUM1};

Somehow this seems counter-intuitive. I thought that the reason that the apostrophe was added to the curly braces was to distinguish the assignment pattern from concatenation. And then we use the concatenation syntax for an empty set of elements.

I have tested the

other_enum_t      _b [] = '{};

code with the Cadence and Aldec simulators and it passes without warnings, so now I am unclear on the whole situation.

4

In reply to evilpascal:
When have a simple set of items, including the empty set, you can always use an array concatenation {} to make an assignment any kind if unpacked array. There is no need to use an assignment pattern for anything you are writing. Use assignment patterns when you need replication, explicit types, or indexing of elements.

Use of an assignment pattern with an empty set of items is illegal according to SystemVerilog BNF. It seems that all tools allow this as an extension, but one tool is reporting it as a warning.

5

In reply to dave_59:

As always, thank you for the explanation.