Dynamic array of components

SystemVerilog
1

I am here trying to create a 2D array of pixel sensors. I want the size of the array to be dynamically chosen by changing the localparam PIXEL_ARRAY_WIDTH and PIXEL_ARRAY_HEIGHT. I can’t seem to get the code to work. I get the following error when compiling:

iverilog -g2012 -Wall -o pixelArray.out pixelArray_tb.v
Assertion failed: ((msb == 0) || (lsb != 0)), function elaborate_scope_mod_instances_, file elab_scope.cc, line 1393.
sh: line 1: 12438 Done /usr/local/Cellar/icarus-verilog/11.0/lib/ivl/ivlpp -L -Wredef-chg -F"/var/folders/y7/str5z30s4lq1hd9vvv9c0sk40000gn/T//ivrlg2c75448c" -f"/var/folders/y7/str5z30s4lq1hd9vvv9c0sk40000gn/T//ivrlgc75448c" -p"/var/folders/y7/str5z30s4lq1hd9vvv9c0sk40000gn/T//ivrlic75448c"
12439 Abort trap: 6 | /usr/local/Cellar/icarus-verilog/11.0/lib/ivl/ivl -C"/var/folders/y7/str5z30s4lq1hd9vvv9c0sk40000gn/T//ivrlhc75448c" -C"/usr/local/Cellar/icarus-verilog/11.0/lib/ivl/vvp.conf" – -
make: *** [pa] Error 134

Does anyone have any idea why this doesn’t work? I am quite new to SystemVerilog so it might be a lack of knowledge about how it works. Thanks for any help!


`include "config.v"
`include "pixelSensor.v"

module PIXEL_ROW(
   input logic      VBN1,
   input logic      RAMP,
   input logic      RESET,
   input logic      ERASE,
   input logic      EXPOSE,
   input logic      READ,
   input logic enable,
   input [7:0] COUNTER,
   output [7:0] DATA_OUT [PIXEL_ARRAY_WIDTH-1:0]
);

    PIXEL_SENSOR pixel_row[PIXEL_ARRAY_WIDTH-1:0] (VBN1, RAMP, RESET, ERASE, EXPOSE, READ, DATA_OUT);

endmodule // PIXEL_ROW

module PIXEL_ARRAY;

    logic analog_bias;
    logic analog_ramp;
    logic analog_reset;

    logic erase;
    logic expose;
    logic read;
    logic enable [PIXEL_ARRAY_HEIGHT];
    tri[7:0] counter;
    logic [7:0] DATA_OUT [PIXEL_ARRAY_WIDTH-1:0][PIXEL_ARRAY_HEIGHT];

    PIXEL_ROW pixel_array [PIXEL_ARRAY_HEIGHT] (
        analog_bias, 
        analog_ramp, 
        analog_reset, 
        erase, 
        expose, 
        read,
        enable,
        counter,
        DATA_OUT
    );

endmodule // PIXEL_ARRAY
2

In reply to Reingb:

A couple of issues with your question and code.

Your code does not show the declarations of the localparams or how they get their values. Typically they are declared in the module definition header and their values set by overrides when you instantiate that module.

The term “dynamic” is used for objects whose values are set a run-time and can usually be changed over the course of a simulation. Parameters (and localparams) are set during compilation and elaboration and cannot change once simulation begins.

You declared DATA_OUT as a 2-D array in PIXEL_ARRAY and connected it to the DATA_OUT port of PIXEL_ROW, which is a 1-D array. That is an incompatible connection. Having an array in a port connection is a SystemVerilog feature that iverilog might not support. It was not allowed in Verilog.