DUT instantiation connection in TB

SystemVerilog
1

Hi all.,
I have one query in DUT instantiation in SV testbench.

  • Below is an example of position based DUT instantion
    RTL_DUT <instance_name> (a,b,c);
  • For instantion by name.,
    RTL_DUT <instance_name> (.a(a), .b(b), .c(c));
  • But what happens when instantiated as below.,
    RTL_DUT <instance_name> ( .* );

What does only “.*” means in above typr of instantiation, please let me know.

2

In reply to iamyash1234:

See section 23.3.2.4 Connecting module instances using wildcard named port connections ( .)* in the IEEE 1800-2017 SystemVerilog LRM.