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  • DUT instantiation connection in TB.

DUT instantiation connection in TB.

SystemVerilog 6318
iamyash1234
iamyash1234
Full Access
28 posts
January 16, 2023 at 9:20 am

Hi all.,
I have one query in DUT instantiation in SV testbench.
* Below is an example of position based DUT instantion
RTL_DUT (a,b,c);
* For instantion by name.,
RTL_DUT (.a(a), .b(b), .c(c));
* But what happens when instantiated as below.,
RTL_DUT ( .* );

What does only ".*" means in above typr of instantiation, please let me know.

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dave_59
dave_59
Forum Moderator
10661 posts
January 16, 2023 at 11:01 am

In reply to iamyash1234:

See section 23.3.2.4 Connecting module instances using wildcard named port connections ( .*) in the IEEE 1800-2017 SystemVerilog LRM.

— Dave Rich, Verification Architect, Siemens EDA

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