I came across the below code for dual port ram.
what does rd_data_2[(i+1)minWIDTH-1:iminWIDTH] <= RAM[{addr_2, lsbaddr}]** mean in this code?
is there any bug in this code?
module ram_dual_port#(
parameter WIDTH = 16,
parameter DEPTH = 1024,
parameter ADDRWIDTHA = $clog2(DEPTH),
parameter WIDTHB = WIDTH,
parameter DEPTHB = DEPTH,
parameter ADDRWIDTHB = $clog2(DEPTHB)
) (
input clk1,
input clk2,
input wr_valid_1,
input wr_valid_2,
input [ADDRWIDTHA-1:0] addr_1,
input [ADDRWIDTHB-1:0] addr_2,
input [WIDTH-1:0] wr_data_1,
input [WIDTHB-1:0] wr_data_2,
output reg [WIDTH-1:0] rd_data_1,
output reg [WIDTHB-1:0] rd_data_2
);
`define max(a,b) {(a) > (b) ? (a) : (b)}
`define min(a,b) {(a) < (b) ? (a) : (b)}
function integer log2;
input integer value;
reg [31:0] shifted;
integer res;
begin
if (value < 2)
log2 = value;
else
begin
shifted = value-1;
for (res=0; shifted>0; res=res+1)
shifted = shifted>>1;
log2 = res;
end
end
endfunction
localparam maxSIZE = `max(DEPTH, DEPTHB);
localparam maxWIDTH = `max(WIDTH, WIDTHB);
localparam minWIDTH = `min(WIDTH, WIDTHB);
localparam RATIO = maxWIDTH / minWIDTH;
localparam log2RATIO = log2(RATIO);
reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
reg [WIDTHB-1:0] readB;
genvar i;
always @(posedge clk1)
begin
if (wr_valid_1)
RAM[addr_1] <= wr_data_1;
rd_data_1 <= RAM[addr_1];
end
generate for (i = 0; i < RATIO; i = i+1)
begin: ramwrite
localparam [log2RATIO-1:0] lsbaddr = i;
always @(posedge clk2)
begin
rd_data_2[(i+1)*minWIDTH-1:i*minWIDTH] <= RAM[{addr_2, lsbaddr}];
end
end
endgenerate
endmodule