Driving signals internal to DUT

SystemVerilog
,
1

Hello,
I want to know how can i drive the transactions to internal sub-blocks of DUT.
Required thing is, driver should access internal signals of DUT.
Thanks,
Nageswar

2

In reply to nag.chil:

Please see Updated Example Code from DVCon Paper: The Missing Link: The Testbench to DUT Connection | Verification Academy