Hi All,
This is the top module which I had designed it is driving the inputs but it is giving some random outputs from the DUT. I’m not able to figure out what’s the mistake in it Can anyone of you guys can help me out with this situation.
`include “DUT.v”
module top;
parameter simulation_cycle = 50;
bit SystemClock;
fir_if arith(SystemClock);
test t1(arith);
fifo dut(.data_in(arith.data_in),
.Data_out(arith.Data_out),
.reset(arith.reset),
.clk(arith.clock)
);
initial begin
$timeformat(-9, 1, "ns", 10);
SystemClock = 0;
forever begin
#(simulation_cycle/2);
SystemClock = ~SystemClock;
end
end
endmodule
I’m driving the inputs in the following manner.
arith.data_in <= generator.data_in
thanks