Driving a bitslice of a virtual interface signal through a task

SystemVerilog
, , ,
1

I’m trying to create a task that’s responsible for setting a bit of a vector and clearing it after one clock cycle. My driver code is attached below:


class my_if_driver extends uvm_driver;
  `uvm_component_utils(my_if_driver)

  // Members
  // UVM stuff
  virtual my_if_interface vif;

  function new(string name="my_if_driver", uvm_component parent);
    super.new(name, parent);
  endfunction

  extern function void build_phase(uvm_phase phase);
  extern function void connect_phase(uvm_phase phase);
  extern task          run_phase(uvm_phase phase);

  extern task drive_my_if(my_if_transaction txn);
  extern task set_then_clear(ref logic signal);
endclass

function void my_if_driver::build_phase(uvm_phase phase);
endfunction

function void my_if_driver::connect_phase(uvm_phase phase);
endfunction

task my_if_driver::run_phase(uvm_phase phase);
  @(posedge vif.resetn);
  forever begin
    seq_item_port.get_next_item(req);
    fork
      drive_my_if(req);
    join_none
    seq_item_port.item_done(req);
  end
endtask

task my_if_driver::drive_my_if(my_if_transaction txn);
  // Wait for delay
  repeat (txn.cycle_delay) @(posedge vif.clk);
  // Then drive appropriate signal
  if (txn.my_if_cmd == my_if_transaction::CMDA) begin
    set_then_clear(vif.my_if_cmd_a[txn.tid]);
  end
  else if (txn.my_if_cmd == my_if_transaction::CMDB) begin
    set_then_clear(vif.my_if_cmd_b[txn.tid]);
  end
  else if (txn.my_if_cmd == my_if_transaction::CMDC) begin
    set_then_clear(vif.my_if_cmd_c[txn.tid]);
  end
endtask

task my_if_driver::set_then_clear(ref logic signal);
  signal <= 1'b1;
  @(posedge vif.clk);
  signal <= 1'b0;
endtask

I get the following errors:

** Error: path_to_driver.svh(53): LHS in non-blocking assignment may not be an automatic variable

** Error: path_to_driver.svh(55): LHS in non-blocking assignment may not be an automatic variable

These point to the non-blocking assignments to ‘signal’ in the set_then_clear task. However, if I pass the whole vector and the tid separately to the task, it doesn’t throw a compilation failure.

Is there a way to point to a bitslice of a virtual interface via a ref argument?