Drive interface port from a task

SystemVerilog
1

Hi sv forum.
In an interface I have a port sys_out;


interface sys (input logic clk);
   logic sys_out;
   ...
endinterface

in an initial process that I have inside the interface I drive the sys_out port;


initial begin
   forever begin
      @(posedge clk) begin
         sys_out<=1'b1;
         #1;
         sys_out<=1'b0;
         #1;
         sys_out<=1'b1;
      end
   end
end

At this format my code works as expected.
Now I want to write a task which wiggle the sys_out port because this code repeat it self in many places
So I wrote a task code


task do_something(input bit init_value, output logic sig);
   sig<=init_value;
   #1;
   sig<=!init_value;
   #1;
   sig<=init_value;
endtask

I changed the initial process to


initial begin
   forever begin
      @(posedge clk) begin
         do_something(1'b1, sys_out);
      end
   end
end

This code is not wiggling the port, why?

In addition this task is been called by many process which are fork…join.
Is it enough to put automatic modifier in the life time place?


task automatic (...);
2

In reply to shimonc:

The problem with your code is that task input arguments copy their value upon entry to the task, and output arguments copy their value upon exit from the task. So only the value from the second of your 3 assignments gets copied to sys_out. You need to use pass by reference arguments instead of pass by value.

See const ref | Verification Academy