Down casting of reg to short int resulting in addition of extra bits that should not be expected

SystemVerilog
,
1

Hi,
Here’s the code:

module top;
  reg [63:0]a1,b1;
  reg [63:0] out1, out2;
  initial begin
    a1 = 64'habcd1234abcd5678;
    b1 = 64'h1234abcd1234efba;
    out1 = shortint'(a1);
    out2 = shortint'(b1);
    $display("out1 = %h ", out1);
    $display("out2 = %h", out2);
  end
endmodule

output:
out1 = 0000000000005678
out2 = ffffffffffffefba

I think the typecasted value of 16 bit (last 4 hex bits) are assigned to out1/out2 which is again a 64 bit reg. The LSB of 16-bit shortint value is taken and the LSB of this typecasted value is replicated to fill the remaining bits of register.
I have the doubt whether this correct as per the LRM ?
Shouldn’t extra LSB bit always be filled with 0 in order to maintain the shorint’() output intact?

2

In reply to Kumar Saurabh:

See the Operators and Expressions part of the Verilog spec.
Noteworthy:
shortint is a signed type.
The assignment is a context-determined expression.

The verilog assignment rules indicate that the right hand signed will be extended to the left hand side length “performing sign extension if, and only if, the type of the right-hand side is signed.”

There’s all sorts of special cases documented fairly well in that section of the spec with regard to bit-lengths and signedness. One must be careful when crossing different bit-sizes, with different signedness, with various operations. There can be subtle bugs here.

Regards,
Mark