Doubt in assignment opeartors

SystemVerilog
,
1 

module ass_op;

bit [3:0]a=4'hF;
bit [3:0]b=4'b111z;

initial begin 

if(a=?=b) $display("a==?b");
if(a=?=4'b111z) $display("a==?4'b1x1z");
if(b =?=a)$display("b==?a");
end

endmodule

Result is # a==?4’b1x1z .
Why first if loop display is not coming?

2

for “==?” operands to be in integral. Try using “integer”.

=?= are not present in LRM.

3

In reply to kranthi445:

for “==?” operands to be in integral. Try using “integer”.
=?= are not present in LRM.

module ass_op;
 
bit [3:0]a=4'hF;
bit [3:0]b=4'b111z;
 
initial begin 
 
if(a==?b) $display("a==?b");
if(a==?4'b111z) $display("a==?4'b1x1z");
if(b ==?a)$display("b==?a");
end
 
endmodule

I got same result with ==? also …

4

In reply to rakesh reddy:

for ==? operands to be in integral. try logic too[which can hold X or Z]. Bit can not hold X or Z

module ass_op;

integer a=4’hF;
integer b=4’b111z;

initial begin

if(a==?b) $display(“a==?b”);
if(a==?4’b111z) $display(“a==?4’b1x1z”);
if(b ==?a)$display(“b==?a”);
end

endmodule

5

*In reply to rakesh reddy:*b needs to be declared with a 4-state to hold a ‘z’ state. Try

module ass_op;
 
bit [3:0]a=4'hF;
logic [3:0]b=4'b111z;
 
initial begin 
 
if(a==?b) $display("a==?b"); //match
if(a==?4'b111z) $display("a==?4'b1x1z"); // match
if(b ==?a)$display("b==?a"); // no match
end
 
endmodule
6

Hi Rakesh Reddy,

you are declaring a and b as bit type so it will treat x and z as 0. so it the first statement is not getting printed. If you use logic as data type you can observe all three statements.

Thanks