Doubt about driving signals from driver class to interface or dut

I m creating systems verilog verificaton architecture for full adder,
And this full adder (dut)will give sum and carry out at posedge,
While driving signals from driver to interface or dut without using delay I m not getting
output what is the reason for that?
Example—>

    @(posedge vih.clk)//vih means virtual interface handle
        Vih.in1<=trans.in1;
       Vih.in2<=trans.in2;

In reply to Mallikarjun:

Cannot possibly help you with that tiny piece of code. You need to learn your tools debugging capabilities and either single step through the code, or watch signals values change in a waveform.