Dollar($) Sign in Variable Names

SystemVerilog
1

Hi.

Verilog or SystemVerilog allows dollar($) sign in variable names.
Is there a specific reason it is allowed?
What is the common use case of a dollar sign in variable names?

Thanks.

2

In reply to Jung Ik Moon:

Normally, we use $ sign for built-in system taak/function.Such as: $time, $display, $rose, $fell, etc…

3

In reply to chris_le:

What about the cases other than system tasks/functions?
What could be other use cases of using a dollar sign in variable/task/function names?
For example, below code is legal for SystemVerilog.

class my_class;
    int var$;
    int hello$world;
    function void func$name();
    endfunction
endclass: my_class
4

In reply to Jung Ik Moon:

They are normal variables/functions because SV allows $ sign in variables/functions. Just one of many ways to declare them, there are no specific reason, I think.

5

In reply to chris_le:

Thanks Chris