I have some questions regarding other verification stuffs like the importance of linting, issues in gate level netlist, formal verification, CDC verification, static vs functional verification, low-power verification, etc… but we do not have any Forum Category for these topics. Does Verification Academy have any plans to add it? If not, where should I post questions like these?
In reply to Reuben:
I suggest www.edaboard.com, especially ASIC Design Methodologies and Tools or
PLD, SPLD, GAL, CPLD, FPGA Design.