Display portion of the variable

SystemVerilog
1

I have a 64 bit variable and occasionally I want to use it for 32 bit variable. Now when printing the variable it prints whole 64 bits, but in case when I use for 32 bit purpose, I want to just print the lower half of 64 bits .

For example,

bit [63:0] var_64;
var_64 = 64'h1234_5678_aaaa_bbbb;
$display("var = %x",var_64); This is displaying "1234_5678_aaaa_bbbb" , which is good
var_64 = 32'h1234_5678;
$display("var = %x",var_64); This is displaying "0000_0000_1234_5678" , but I want just lower 32 bit "1234_5678" , and not 0s in front.

Thank you,
Mega

2

In reply to megamind:

$display("var = %x",var_64[31:0]);
$display("var = %x",32'(var_64));
3

In reply to dave_59:

Thank you Dave. Is there any way to play with %4x or %8x etc, something like that, without casting or part select, as originally I was thinking that it is possible to control the precision points. This is just for curiosity otherwise solution is going to work.

4

In reply to megamind:

If you can guarantee the upper bits are all zero, then %8x would also work. Remember that %8x is interpreted to be the minimum field width. If any of those upper bits are non-zero, they would be displayed.

5

In reply to dave_59:

That is perfect! and that was the solution I was actually looking for, somehow I got confused earlier on the interpretation of %8x etc, but now its better clear. Thank you very much Dave.