Display the periods of several clocks when ever they changes the period

Hi All,

I Want to find the period of several clocks when even they changes the time period.

For that write a verilog module like this
// RTL

module CLOCK_PERIOD(clock,str);
  input clock;
  time Period;
  input reg [50*8:0] str ;
  time  previous_time;
  
  always @(posedge clock)
    begin
      Period = $time - previous_time ;
      previous_time = $time ;
    end
  
  initial begin
    $monitor("Clock Period \t %s =%t ",str,Period);
  end
  
endmodule
// TB
module tb;
  
  bit clock1;
  bit clock2;
  
  CLOCK_PERIOD  RTL1(clock1,"clock1");
  CLOCK_PERIOD  RTL2(clock2,"clock2");  
  
  initial forever #10 clock1 = ~clock1 ;
  initial forever #20 clock2 = ~clock2 ;
  
  initial begin
    #500;
    $finish;
  end
endmodule

output is like this

Clock Period 	                                              clock2 =                   0 
Clock Period 	                                              clock2 =                  40

It is printing the last instantiated module.
but the actual Desired output is

Clock Period 	                                              clock1 =                  20 
Clock Period 	                                              clock2 =                  40

Can any one tell me how to fix this problem.

Thanks,
IGH

In reply to igh:

Do not use
$monitor
. It was intended as an interactive command only for the simplest of debugging.

Convert your initial block to an always.

  always @Period begin
    $monitor("Clock Period \t %s =%t ",str,Period);
  end