Display assertion result of multi bind

SystemVerilog
1

Hi All,

I wrote an assertion to check for 4 modules.
I want to get result of assertion by a File then I used

result_file = $fopen("result_assertion.txt", "w");

and

$fdisplay (result_file,"module A pass")

to display result assertion pass or fail

The issue is I have to bind 4 modules into this assertion so the result display is overlap.
For example: all 4 modules is passed the assertion.
My expected result_file.txt :

module A pass
module B pass
module C pass
module D pass

But the real result_file.txt will be write overlap something like this:

pass
module C pass

Do you have any idea for this issue.
Thanks and Best regards.

2

In reply to yukinon309:
Create a common package

package assert_report;
  int result_file;
  function void open;
    if (result_file) return; // file already opened
    if (!(result_file = $fopen("result_assertion.txt", "w") )
      $error("Could not openresult_assertion.txt");
  endfunction
  function void print(string message);
    $fdisplay (result_file,nessage);
  endfunction
endpackage

Then in your bound module, call assert_report::open() and assert_report::print()