Disabling assertion until clock edge

SystemVerilog
,
1

I want to disable an assertion until a clock edge (posedge or negedge occurs). Can anyone help me in this regard?

2

The easiest way is to add supporting code that detects the enabling condition, and use that in the disable iff. Thus,


module m; 
	bit a=1, b=1, go, clk; 
	initial begin 
		#100;
	    forever #5 clk=!clk; 
	end 
	ap_ab: assert property (@ (posedge clk)
       disable iff (!go) // if go==0, cancel checking asynchronously
              a |=> b);
	initial @(negedge clk) go <= 1'b1;  
	
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
3

In reply to pRoSpEr:

How about $assertoff?


initial begin : aoff
  $assertoff();
  @(posedge some_global_clk);
  $asserton ();
end : aoff

Regards
Srini
www.verifworks.com