Disable SVA on a Fail

SystemVerilog
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1

I have SVAs that performs check on each clock cycle. Once there’s violation, these checks fail on each cycle cluttering output log. Is there any way to disable an assertion once there is a fail?

2

You can use $assertoff or $assertkill in the else part of the assertion. The following code works for me.

DETECT_GLITCH : assert property (detect_glitch)
else
  $assertoff(0,DETECT_GLITCH);

// Output
"testbench.sv", 21: top.DETECT_GLITCH: started at 3ns failed at 3ns
	Offending 'top.my_func()'
Stopping new assertion attempts at time 3ns: level = 0 arg = DETECT_GLITCH (from inst top (testbench.sv:23))

Refer here for a similar question. Refer IEEE 1800-2012 Section 20.12 for system tasks of assertions.

3

In reply to sharvil111:

Great! Thanks a lot.