Disable iff in immediate assertion

SystemVerilog
, ,
1

Hello,

Can I use disable iff in an immediate assertion? Example code below

always @(signal1)	
begin
example: assert ( disable iff(signal2 === 3'b011) $rose(signal3) |-> $rose(signal4) );
else $error ("ERROR");
end
2

In reply to sj1992:

Did you try it?

You cannot use disable iff or $rose (or any sampled function) because there is no inferred clock—it is instantaneous.

3

In reply to dave_59:

Then what should we use to disable immediate assertion instead of disable iff ?
like : disable iff ( reset==1’b1 || $isunknown(reset)

4

In reply to Himanshu m soni:

An immediate assertion is just a procedural statement, not a process that needs to be disabled. You can use a conditional branching statement like if to avoid executing it.

5

In reply to dave_59:

Thanks a lot Dave