Difference between program and module

SystemVerilog
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1

Hai sir, just now i posted one question.while i am checking the answer but that question is not there in my account previously same thing happened ,please check it sir.
sorry for again asking my question
A program definition can occur within a module
module tb;
bit [3:0] mode;

program p1;
…
endprogram

program p2;
…
endprogram
endmodule
module inside the program block is allowed or not and program block inside module is allowed.
both are not allowed
I sea above code in chipverify.com
below is the link
SystemVerilog Program Blocks

2

In reply to anvesh dangeti:

A program block is a legacy construct that has several significant issues when used. You should not use any program blocks and use modules instead.