Difference between program and module

SystemVerilog
,
1

what is exact difference between program and module.
when i compiled below program

program main;

module ma;
endmodule

endprogram

ERROR:: a module can only be declared at the compilation unit top level, or within a module [SystemVerilog].

And have seen that program cannot contain always block.

I need to know why program is introduced in sv and how to exactly use it?

2

Forget about them. http://go.mentor.com/programblocks

3

In reply to cgales:

Thank you…