The difference between value of an input clockvar and the raw signal is straightforward ,
At each clocking event the input clockvar are internally updated by the clocking block . The DUT updates the raw signal on the same clocking event .
however I am trying to figure out difference between output clockvar and the raw signal since they are manually assigned / driven by DV owner
Consider the following code ::
module Top;
bit clk ;
bit [1:0] to_DUT ; // Raw signal defaults to 0
clocking cb @( posedge clk );
default input #1step output #2;
output to_DUT ;
endclocking
always #5 clk = !clk ;
initial begin
#3 cb.to_DUT <= 3 ;
end
initial #20 $finish() ;
endmodule
From what I understand :
The raw signal ’ to_DUT ’ is scheduled to be driven in Re - NBA region of time 7 units ( clocking event at t : 5 + output skew of 2 units )
However the following isn’t clear :
When is the output clockvar ’ cb.to_DUT ’ driven ?
Is it driven in Re - NBA region as well ? Does the drive occur relative to clocking event and output skew ?
A colleague suggests that output clockvar ’ cb.to_DUT ’ is driven in Re - NBA region of time 3 units ( independent of clocking event and output skew ) ,
however I am not a 100% certain on it .
On adding ::
always @( cb.to_DUT ) $display(" Output clockvar cb.to_DUT changes at T:%2t ",$time);
I observe different results across tools .
One of the tool throws a compilation error ( maybe since output clockvar is being read )
2nd tool doesn’t throw compilation error and the display statement executes at T: 3 ( i.e same time as execution of the drive independent of clocking event and output skew )
3rd tool doesn’t throw compilation and the display statement executes at T: 7 ( i.e after clocking event and output skew )