Difference between input and wire clock to an interface

Hi,

Is there a difference if the main clock of the interface, the clock that used as a clock for the clocking clock define as input or if it is define as a wire and get his value with assign statement.
Or in other words Does it optional an interface that his clock define as a wire and this interface has clocking block?

Regards.

In reply to rraa:

I cannot make any sense of your question. Can you add some code examples that back up what you are trying to ask?

In reply to dave_59:

First thanks to for your answer.

I am trying to add a light bus that will replace an existing VIP, the interface of the VIP doesn’t give the clock of the interface as input but assign as a wire, in order to avoid ifdef I want to connect the clock of the light bus same.

**So want I need to know if there is any difference between both below examples.
**
Example 1, clk is wire:
Declare the interface:
light_bus_if bus_if();

assign the clk:
bus_if.clk = `TOP.clk;

in the interface:
wire clk;

clocking cb @(posedge clk);

Example 2, clk is input:
Declare the interface and give the clock :
light_bus_if bus_if(.clk(`TOP.clk));

in the interface:
interface light_bus_if (input bit clk)

clocking cb @(posedge clk);

Thanks

In reply to rraa:

OK, that is much clearer now. You have two separate questions.

The first is what is the difference between declaring a signal internal to an interface (which I assume you declared clk that way in example 1), versus declaring a signal as a port of an interface?

You would typically declare signals internal to an interface if you want each instance of that interface to have a different values for each instance. And you would declare signals as ports of an interface if you wanted to share that signals value across other instances (same interface or different interfaces or modules). A shared clock would be a good candidate for this.

The use of clocking blocks is independent to ports versus internal signals. My opinion on that is not to introduce them until you have a specific problem that you know you can solve.

Hi,

So according to what you said.

It is recommended to declare a signal as an input if it is a signal that is same for other interfaces/modules.
But in anyway it can be declared as a wire.

In my case I create some instances of the same interface in generate loop and one of them get other clk than the others, so I have to declare the clk as a wire.

Thanks.