Difference between codes

SystemVerilog
1

Hi,

I can’t understand what the difference ?

Between this:

 output logic o[2:0],
  input logic clk,
  input logic d,
  logic o1,o2,o3;

   always_ff  @ ( posedge clk)
         o1 <= d;
   always_ff  @ (posedge clk)
         o2 <= o1;
  always_ff  @ (posedge clk)
         o3 <= o2;

    assign o[0] = o1;
    assign o[1] = o2;
    assign o[2] = o3;

and this:

   always@(posedge clk)
       o <= {o[1:0],d};

?

2

In reply to alexd555:

The difference is in the number of lines of code used to describe the same behavior.