Hi,
It is very strange that @time 15, AAA’s negedge can’t be see when clocking event is triggered, but change clocking event(@(vif.cb)) to its actual clock(@(poedge clk)) as event，it will see AAA’ negedge, Is there anyone who can tell me why?
interface itf;
logic AAA;
logic clk;
logic AAA_d;
always @(posedge clk)
AAA_d <= AAA;
clocking cb @(posedge clk);
default input #0.1 output #0.1;
input AAA;
endclocking
endinterface
module top();
reg AAA;
itf vif();
initial begin
clk = 0;
AAA = 0;
#4;
AAA = 1;
#10;
AAA = 0;
end
always #5 clk = ~clk;
assign vif.clk = clk;
assign vif.AAA = AAA;
initial begin
forever begin
@(vif.cb) begin //issue here, change to @(vif.clk) is ok
if(~vif.AAA && vif.AAA_d) do something... //it can't see negedge if waiting vif.cb otherwize vif.clk is ok
end
end
end
endmodule