Difference between @cb and @posedge clk

SystemVerilog
1

Note : Consider clocking block is executed on posedge of the clk.

I know , you might be feeling there is no difference. Trust me, I also felt same until I came across this thing.

Example :

  • If @cb is invoked on first posedge of the clk then, it will immediately come out on same posedge only causing no clk delay.
  • If @(posedge clk) is invoked on first posedge of the clk then, it will come out on second posedge causing one clk delay. (this is expected)

I could not find the document explaining reason for such difference.

Can anyone explain?

2

In reply to supal:

There is some difference in that the @cb event does not get scheduled until the observed region. Depending the code written, you may or may not see a difference. My guideline is once you start using clocking block events, do not mix them with any other kinds of events.

3

In reply to dave_59:

Thanks for the reply. Can you elaborate a bit more on what kind of difference ? Probably any example would clarify this.

4

In reply to supal:
Example in section 14.13 Input sampling

clocking cb @(negedge clk);
  input v;
endclocking
always @(cb) $display(cb.v);
always @(negedge clk) $display(cb.v);

The preceding first always procedure is guaranteed to display the updated sampled value of signal v. In contrast, the second always exhibits a potential race and may display the old or the newly updated sampled value.

5

I still don’t quite understand the transition of each region in the timeslot during simulation. I have two questions about this:

  1. Is there any relationships between the timeslot and the clock-cycle in the simulation? Is the timeslot a detailed division of the execution sequence for each clock edge？
  2. What happens after @(cb) is scheduled in the observed region? Will the clock advance to the next clock edge?
6

In discrete event simulation, atime slot is all regions executing with the time at the same value before advancing time to its next value. In general, there are many time slots between each clock cycle @(posedge clk). But it is very easy to write code that generates multiple clocks cycles in the same time slot. This code iterates the clock between the active and NBA regions.

module top;
  bit clk;
  initial begin
    #1 clk <=1;
    repeat(20) @clk clk<=!clk; // all within one time slot
    #1 clk<=!clk;
    repeat(20) @clk clk<=!clk;
  end
  always @(posedge clk) $display($time,"  posedge");
endmodule

The clocking block code in the previous post does not show how the clock gets generated. The only concept that advances is time. We wait for clock events.

7

T hank you very much, but I still have a few questions about the above example:

  1. It was mentioned earlier that @clocking_block is scheduled in the observed region, so in what region is @(posedge clk) or @event scheduled?
  2. The comment in the above code says “all within one time slot”，does this mean that if time does not advance, then the regions within the current time slot will continue to execute in sequence 20 times?
8

Event controls are interprocess communication. There are at least two processes involved; the one triggering the clk value change or named event, and the others waiting on the trigger. The trigger can happen in any number of regions depend on which construct is used to cause the triggering. Normally it will be in the active or NBA regions. The resume from waiting occurs in the process waiting for the trigger. That occurs in the active region (unless you use the unrecommended program block).

You should try the code to answer your second question on EDAPlayground.com

9

Thank you very much for your explanation