In reply to prashantk:
Quote:
can someone please explain the difference between the two assertions.
Though I am delighted that you intend to use assertions in your specification and verification process, I am concerned that in asking such a basic question, you have not really taken the time to study SVA. There are many books (
including mine) that cover the subject. There are also many videos and sites that explain SVA. I suggest that you take the effort.
The point: There is a lot more to SVA than you think.
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Ben Cohen
http://www.systemverilog.us/
*
SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
*
Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
* Component Design by Example ", 2001 ISBN 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
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