Difference between a ##5 b and a |->##5 b

SystemVerilog
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1

can someone please explain the difference between the two assetions.

2

In reply to prashantk:

The first will be checked at every posedge of clk and second will be checked at only if a is true.

3

In reply to prashantk:
Neither one of them are assertions by themselves. The construct
a ##5 b is just a sequence that says “a is true, and 5 clock cycles later, b is true”. If you were to use that sequence in a concurrent assertion, it would become

assert property (@(posedge clk) a ##5 b);

The would mean at every clock cycle, a has to be true, and 5 clock cycles later b has to be true. But this essencially means a has to be true all the time.
The construct
a |-> ##5 b is a property that says "When a is true, b must be true 5 clock cycles later.
This used in a concurrent assertion would become

assert property (@(posedge clk) a |-> ##5 b);

Now only on the clock cycle when a is true is there a requirement that b be true 5 cycles later.

4

In reply to dave_59:

Thanks for the reply dave_59.

Can we apply assertions inside if else ?

5

In reply to prashantk:

can someone please explain the difference between the two assertions.

Though I am delighted that you intend to use assertions in your specification and verification process, I am concerned that in asking such a basic question, you have not really taken the time to study SVA. There are many books (including mine) that cover the subject. There are also many videos and sites that explain SVA. I suggest that you take the effort.
The point: There is a lot more to SVA than you think.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us