Design keyword is actually a verilog keyword.
The term design indicates which module to use. The term can only be used within a config statement.
Currently it is used with a library.
Example design <lib_name>.top
‘lib_name’ is the testbench library.
‘top’ here is the top_level of a testbench.
Here is it setting lib_name as the top module.
In the dve window it starts elaborating from the top.
How do I change the top to a different module, say like a design_Top excluding the testbench?
Can I get an example of how to use this design keyword?
The config name ‘cfg1’ is essentially an alias for rtlLib.top, except the top.a2 module uses the gateLib library version instead of the rtlLib version.
To simulate, you would specify ‘cfg1’ as the top level simulation block instead of ‘top’.