Depending on one of the variable, I want to control the `define values

SystemVerilog
1 

task bit_dec(bit b);
if(b)
begin
   `define GC_TAG_ADDR_RANGE 35:16
   `define GC_TAG_WIDTH       20
end
else
begin
   `define GC_TAG_ADDR_RANGE 35:17
   `define GC_TAG_WIDTH       19   
end

in this condition, even b value is 1, GC_TAG_WIDTH and GC_TAG_ADDR_RANGE value getting 19 and 35:17 respectively. can anyone suggest the way to control the `define value depending on the requirement?

2

In reply to Peram Ravi:

A `define is a compile-time directive. You can’t change them procedurally.

3

In reply to Peram Ravi:

It would also help to show what your intent was to do with such macros. What is your actual problem that this was an attempt to solve.