Hi i wanted a suggestion where i need to create a situation as follows in system verilog:
I have to increment a value say "t" uptill n1 or less,
and simultaneously decrement "t" whenever i get a signal x high can say posedge of x , and as the "t" gets less than n1 because we decremented it as we got posedge of x. we need to again increment the value of "t" as it became less than n1 because of this decrement..so this dependency goes on forever..we dont have a goto in sv which we could have used..
So overall there is a dependency between getting the signal x high and decrementing and incrementing the value "t".
Any suggestions how can i formulate this is sv.. as i am confused to take care of the dependencies that are involved in this..