Delay in signals at clocking block hierarchy w.r.t RTL hierarchy in waveform

SystemVerilog
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1

There is a testbench env and I am working on some tests, I noticed that in the waveform if I pull a specific signal which is input to rtl from rtl hierarchy and pull the same signal from the driver clocking block, I see that the signal at rtl hierarchy is one clock delayed as compared to the same signal at the driving clocking block hierarchy while if I pull out a signal in waveform which is output from rtl at rtl hierarchy and the same signal at the monitor clocking block hierarchy, I see the same signal at monitor clocking block level is delayed by one cycle.

Are the signals at monitor clocking block level always delayed and at driver clocking block level always come one clock early with respect to the signals seen at rtl hierarchy?

The prototype of interface is like this :

         interface my_if(input bit clk, bit reset);
         bit valid;
         bit [31:0] data;
         bit [2:0]  crdt; 


          clocking monitor_cb @(posedge clk); 
          default input #1 output #1; 
          input valid; 
          input data;
          input crdt;
          endclocking 

          clocking tx_driver_cb @(posedge clk); 
          default input #1 output #1; 
          output valid; 
          output data;
          input crdt;
          endclocking 

          clocking rx_driver_cb @(posedge clk); 
          default input #1 output #1; 
          input valid; 
          input data;
          output crdt;
          endclocking 

       modport tx_driver (clocking tx_driverv_cb);
       modport rx_driver (clocking rx_driver_cb);   
       modport monitor (clocking monitor_cb);

        endinterface
2

In reply to GC:

Just by looking into your interface it is difficult to guide you for anyone.
I will try to explain probable cause of this issue.

I am assuming you are using non blocking inside your driver.

So, as we know RSH part of non blocking assignment eveluat in active region.
And assignment from RSH to LHS done in NBA region for non blocking assignment.
So,you will not able to see same change inside RTL at same clock.
I hope it helps.



//Driver
@(tx_driver_cb)
tx_driver_cb.tx_driver.crdt <= 1;

//DUT
@(posedge clk)
crdt_reg <= crdt;

Thanks,
Harsh