Delay a signal by a certain period and also get the opposite polarity of the signal as output?

I am new to System Verilog.

I wanted to delay a signal by certain period (say a period of 100ms) and also get the output as reverse polarity.
Thanks in advance,

In reply to nijo:

module delay_signal(input signal, output logic delay_reverse_polarity);

  always_comb delay_reverse_polarity <= #100ms ~signal;

endmodule

Thankyou!
I am using System Verilog to write the RTL. And we cannot use #100ms in the RTL code. Would there be a way to realize this in RTL?

thanks in advance,

In reply to nijo:

I had a feeling there was more to this question. There are many more requirements one needs to know in order to implement this in RTL. Typically this is implemented using a shift register.