This is my first post in this forum so I am sending greetings to all members of this forum.
I´ve made a small traffic light controller project. The circuit is basically controlled by a clock. So after X clk posedges the state changes.
I´ve also included a push-button for the pedestrians to switch the lights faster. But at the moment the state changes immediately when the button is pressed.
I would prefer to delay the execution of the push-button signal somehow by X clk posedges, so that the lights for the cars have a minimal green phase.
code extract:
always @(posedge clk or negedge reset)
begin
if(~reset)
begin
state <= S0;
count <= 0;
end
else
case(state)
S0: if(~pushbtn)
begin
state <= S1;
count <= 0;
end
else if(count < sec5)
begin
state <= S0;
count <= count + 1;
end
else
begin
state <= S1;
count <= 0;
end
S1: if...
Welcome. This forum is mainly for writing verification code, not design code. But many of the same skills are required.
You can use another counter, or you can change the counter limit when to move to S1.
always @(posedge clk or negedge reset)
begin
if(~reset) // active low
begin
state <= S0;
count <= 0;
walk <= 1;
end
else
case(state)
S0: if(~pushbtn) // active low
walk <=0; // active low
if(count < (walk ? sec5 : sec1))
begin
state <= S0;
count <= count + 1;
end
else
begin
state <= S1;
count <= 0;
walk <= 1;
end
S1: if...
Hello @ all
This is my first post in this forum so I am sending greetings to all members of this forum.
I´ve made a small traffic light controller project. The circuit is basically controlled by a clock. So after X clk posedges the state changes.
I´ve also included a push-button for the pedestrians to switch the lights faster. But at the moment the state changes immediately when the button is pressed.
I would prefer to delay the execution of the push-button signal somehow by X clk posedges, so that the lights for the cars have a minimal green phase.
In my SVA Handbook I provide in the chapter on formal verification an example of a traffic controller.
I recommend that you use assertions to understand your requirements.
What you are trying to express is not a delay in execution of the pedestrian button, but rather defining a minimum number of cycles in which a light must sustain is state. That is done with a counter.
Below is an assertion that expresses this notion
// The NorthSouth light is the main street light.
// It must remain GREEN for ns_green_timer == 3 before it can switch.
// Timer ns_green_timer will count to 3, and remain at 3 until light changes.
property NsGreenForMin3Ccyles;
@ (posedge clk) disable iff (!reset_n || emgcy_sensor)
$rose(ns_light==GREEN) && !$past(emgcy_sensor) |=>
ns_light==GREEN[*2];
endproperty : NsGreenForMin3Ccyles
NsGreenForMin3Ccyles_1 : assert property (NsGreenForMin3Ccyles);
Code would have something like:
// NS Counter
always @ ( posedge clk )
if (reset_n==1'b0 || ns_state==YELLOW || ew_2red_cmd == 1'b1) ns_green_timer <= 2'b00;
else if (ns_green_timer != 2'b11) ns_green_timer <= ns_green_timer + 2'b01;
....
case (ns_state) ....
GREEN : begin
if (emgcy_sensor_r==1'b1 || (ew_green_req==1'b1 && ns_green_timer==2'b11))
next_ns_state=YELLOW;
if (emgcy_sensor_r==1'b1) emgcy_sensor_ack=1'b0;
end
Thank you both very much for these great answers.
Excuse me for responding that late, I had to help out at work.
As you might have noticed I am very new to systemverilog and hardware programming so I really appreciate your advices. I am going to have access to an fpga on monday, so I am looking forward to use your improved code. :)
@dave_59
Yes, perfect, this is exactly what my code needed. Thank you so much.
I am also curious about the solution with the second counter. If you could post also this version that would be awesome. :)
@ben@SystemVerilog.us
Yes, you are absolutely right. I just wasn´t able to express myself properly.
As I am new to SystemVerilog I had to look up some few things to understand your code.
But now I mainly got it and its just great and very interesting. I have found favour in hardware programming and I want to learn more about systemverilog so I will surely have a look in your handbook. :)
… @ben@SystemVerilog.us
Yes, you are absolutely right. I just wasn´t able to express myself properly.
As I am new to SystemVerilog I had to look up some few things to understand your code.
But now I mainly got it and its just great and very interesting. I have found favour in hardware programming and I want to learn more about systemverilog so I will surely have a look in your handbook.
Since you plan to migrate to hardware, and you are new to this, I do have a couple of very sincere recommendations because there is a lot more to hardware design than knowing a design language.
Specifically, one needs to know and understand the various uses of things like the a)the types of counters, b) metastability, c) enhancing speed techniques, d)design of an error detection and correction, e) techniques in designing a CPU (microcode or FSM), synchronous and asynshronous FIFOs, etc:
2. Study my book Real Chip Design and Verification Using Verilog and VHDL, 2002In that book I address all these issues. It is available at Amazon (see VhdlCohen Publishing ).
However, at https://www.createspace.com/6334329 for a retail price of$80, with the discount code of 4XG6ECTE that drops the price to $54.40.
This book reflects a lot of my experiences and difficulties in applying an HDL to real designs and verification. Today, I would add assertions, and would stay ith SystemVerilog, but that is a different story.
3. A case in point about some of the tricky things in hardware design is demonstrated in my SVA book (in the formal verification chapter) on the design of complex traffic light controller. The link to those pages is as http://SystemVerilog.us/svabk4_Traffic_light.pdf
In my initial model, I used two loosely coupled FSM machines to control the EW and NS traffic. That got me into a lot of trouble as demonstrated by the assertions. I then switched to a two FSMs master/slave approach, and that worked well, as also verified with the assertions.
Use assertions to clarify your requirements and to check your code. My book provides lots of examples. SystemVerilog Assertions Handbook, 4th Edition https://www.createspace.com/5810350
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Wow, thank you so much for your support and information. I really appreciate it. Your answer shows a good way how to start with the complex topic of hardware programming. Thank you also for the tip with the discount codes. :P