Delay output port signals by a time unit

SystemVerilog
1

Hi There,

Is there a way in systemverilog/verilog we can delay all the outputs by a time unit for simulation?

e.g lets say we have a module

module M(
input logic i_a,
input logic i_b,

output  logic   [31:0]      o_a,
output  logic               o_b);

Can I use some construct to delay o_a and o_b by a time unit lets say 25ns.

Thanks,
Sunil.

2

In reply to KumarSunilB:

See section 30.4.2 Simple module paths in the IEEE 1800-2017 LRM