#delay is not working as expected in system verilog class (timescale issue)

SystemVerilog
,
1

I add #2000ns in my class(actually it’s a UVM test sequence), but it seems that it does not delay 2000ns, I print time before and after this delay, and find that the actual delay is 200ns. And I add a $printtimescale task in this class, then in my log it print:
“TimeScale of $unit is 100 ps / 100 ps”

My question is:

  1. I add timescale in my tb_top.sv: `timescale 1ns/1ps, and I add " -timescale=1ns/1ps " option to my my simulation tool. Why in my class, timescale is 100ps/100ps ?
  2. When I add #2000ns in class, why not 2000ns is delayed? It seems that it treat this sentence as “#2000”, and add 100ps unit, so the result is 2000 * 100ps = 200ns.

Hope somebody can help me, thanks very much!

2

In reply to kranthi445:

Without showing any code, it will be difficult to help you. Specifically, how you came to find the delay was only 200ns.

Also, the `timescale directive does not apply to code in $unit (outside a module). You should put this code in a package and use timeunit construct.

3

In reply to dave_59:
test.sv

class test extends uvm_test;
 task t1();
  $printtimescale; 
  `uvm_info(get_name,$psprintf("Kranthi 1"),UVM_NONE);
   #2000ns;
  `uvm_info(get_name,$psprintf("Kranthi 2"),UVM_NONE);
 endtask
endclass

"TimeScale of $unit is 100 ps / 100 ps
Kranthi1 and kranthi 2 are printed with 200ns gap.

How do i make it work in class? I should keep test.sv in package ?

4

In reply to kranthi445:
It would really help to show a complete example like this:

import uvm_pkg::*;
`include "uvm_macros.svh"
class test extends uvm_test;
  `uvm_component_utils(test)
  function new(string name,uvm_component parent);
    super.new(name,parent);
  endfunction
  task run_phase(uvm_phase phase);
    phase.raise_objection(this);
  $printtimescale; 
  `uvm_info(get_name,$psprintf("Kranthi 1"),UVM_NONE);
   #2000ns;
  `uvm_info(get_name,$psprintf("Kranthi 2"),UVM_NONE);
    phase.drop_objection(this);
 endtask
endclass
module top;
  initial begin
     $timeformat(-9,3,"ns",5);
    run_test("test");
  end
endmodule

This prints

UVM_INFO /home/runner/testbench.sv(13) @ 0.000ns: uvm_test_top [uvm_test_top] Kranthi 1
UVM_INFO /home/runner/testbench.sv(15) @ 2000.000ns: uvm_test_top [uvm_test_top] Kranthi 2
5

Sorry for repeated question, I amm still unclear about timescale

tried small example in edaplayground

class a;
  task b;
    $display("kranthi1 %t",$time);
    #10ns;
    $display("kranthi2 %t",$time);
    #10ps;
    $display("kranthi3 %t",$time);
    #1ns;
    $display("kranthi4 %t",$time);
    #100ps;
    $display("kranthi5 %t",$time);
    #1000ps;
    $display("kranthi6 %t",$time);
  endtask
endclass
module top;
  timeunit 1ps;
  timeprecision 1ps;
   a a1=new();
    initial begin
      $timeformat(-9,3,"ns",5);
      a1.b();
    end
endmodule

output is
kranthi1 0.000ns
kranthi2 10.000ns
kranthi3 10.000ns
kranthi4 11.000ns
kranthi5 11.000ns
kranthi6 12.000n

I am not seeing the 10ps and 100ps delay.

6

Everything changes when I keep timescale

class a;
  task b;
    $display("kranthi1 %t",$time);
    #10ns;
    $display("kranthi2 %t",$time);
    #10ps;
    $display("kranthi3 %t",$time);
    #1ns;
    $display("kranthi4 %t",$time);
    #100ps;
    $display("kranthi5 %t",$time);
    #1000ps;
    $display("kranthi6 %t",$time);
  endtask
endclass
`timescale 1ps/ps
module top;
  timeunit 1ps;
  timeprecision 1ps;
   a a1=new();
    initial begin
      $timeformat(-9,3,"ns",5);
      a1.b();
       $display("kranthi8 %t",$time);
      #10ns;
      $display("kranthi9 %t",$time);
    end
endmodule

output
TimeScale of $unit is 1 ps / 1 ps
kranthi1 0.000ns
kranthi2 0.010ns
kranthi3 0.010ns
kranthi4 0.011ns
kranthi5 0.011ns
kranthi6 0.012ns
kranthi7 0.012ns
kranthi8 0.012ns
kranthi9 10.012ns
V C S S i m u l a t i o n R e p o r t
Time: 10012 ps

#10ns is working differently in class and module. Not sure what is use of timeunit and timeprecision? I thought hardcoded delays are not dependent on timescale. Is there any simple solution for this?

7

Hi,

did you solve the issue?

8

In reply to Hammam:

It is not good programming practice to declare code outside of any module or package, and to have any code using delays without specifying any timescales/timeunits. Although the SystemVerilog LRM says it chooses a tool specific default timescale, I think it should really be an error.

Write the code this way and you will see no issues.

package p;
  timeunit 1ps;
  timeprecision 1ps;
  class a;
  task b;
    $display("kranthi1 %t",$time);
    #10ns;
    $display("kranthi2 %t",$time);
    #10ps;
    $display("kranthi3 %t",$time);
    #1ns;
    $display("kranthi4 %t",$time);
    #100ps;
    $display("kranthi5 %t",$time);
    #1000ps;
    $display("kranthi6 %t",$time);
  endtask
endclass
endpackage
module top;
  timeunit 1ps;
  timeprecision 1ps;
   p::a a1=new();
    initial begin
      $timeformat(-9,3,"ns",5);
      a1.b();
       $display("kranthi8 %t",$time);
      #10ns;
      $display("kranthi9 %t",$time);
    end
endmodule