Delay in assertions using variable

module upd_coverage(input bit clock, input bit reset, input bit a1, input bit a0, input bit ncs, input bit nwr, input bit nrd,

			input bit [7:0]din, input bit start, input bit [7:0]count, input bit err, input bit dir, input bit ec);

bit [7:0]plr;
bit [7:0]ulr;
bit [7:0]llr;
bit [7:0]ccr;

assign plr = upd_top.DUT.plr;
assign ulr = upd_top.DUT.ulr;
assign llr = upd_top.DUT.llr;
assign ccr = upd_top.DUT.ccr;

property p1;
@(negedge clock) ((start)&&(plr < ulr)) |=> (count == plr) ##(ulr - plr) (count == ulr);
endproperty
p1h :assert property(p1);
endmodule

In above code count value increases from plr to ulr value,I was trying to checking the (count == ulr) after the difference between plr and ulr values,but it showing compile error as illegal operand for constant expression.
Can anyone help me how to use delay through this variable

Thanks,
Rajesh

In reply to GEDALA RAJESH:

Consider the following methodology.


http://SystemVerilog.us/vf/sva_delay_repeat_pkg.sv 
package  sva_delay_repeat_pkg;  
  sequence  dynamic_repeat(q_s,  count);   
    int  v=count;   
    (1,  v=count)  ##0  first_match((q_s,  v=v-1'b1)  [*1:$]  ##0  v<=0);   
  endsequence 

  sequence  dynamic_delay(count);   
    int  v;   
    (1,  v=count)  ##0  first_match((1,  v=v-1'b1)  [*0:$]  ##1  v<=0);   
   endsequence 
endpackage 
//The  package can be applied  as  follows:   http://SystemVerilog.us/vf/sva_delay_repeat.sv 
import  sva_delay_repeat_pkg::*; 
module  top;   
  timeunit  1ns;        timeprecision  100ps;     
  bit  clk,  a,  b,  c=1;    
  int  r=2;   
  default  clocking  @(posedge  clk);  endclocking     
  sequence  q1;  a  ##1  b;  endsequence   
  ap_abr:  assert  property(a  |->  dynamic_repeat(q1,  r)  ##1  c);  
  ap_delay:assert  property(a  |->  dynamic_delay(r)  ##0  b);    

Ben systemverilog.us