Defining readable and synthesizable text byte arrays

SystemVerilog
,
1

I want to define some text strings that I can send over a UART in my FPGA. If I were coding this in C, I’d be wanting something like this:

char Prompt1[] = "This is prompt 1";
char Prompt2[] = "This is prompt 2";

So what is the best way to do this in SystemVerilog? My code needs to be FPGA synthesizable.

All I want is a bunch of byte arrays but I don’t want to declare each byte as individual ASCII chars or hexadecimal values like this:

byte prompt1 [0:7]; = '{"a", "b", "c", "d", "e", "f", "g", "h"};

I can’t use packed arrays like this:

bit [0:87] BIT_ARRAY = "Hello world";

I need to use an unpacked byte array so I can access the individual bytes.

I’ve been able to do it as shown in the below link but this will be a very expensive way of doing it:


module Test( input logic reset );

typedef byte STRING[0:255];

byte  promptId;

localparam byte PAGE1 = 1;
localparam byte PAGE2 = 2;
localparam byte PAGE3 = 3;

function STRING getStr();
    int i;
    string txPage1 = "Page 1";
    string txPage2 = "Page 2";
    string txPage3 = "Page 3";
    
    STRING str = '{default:0};  // Initialise all elements with 0

    if( promptId == PAGE1 )
    begin
      for(i=0; i<txPage1.len(); i++)
        str[i]=txPage1[i];
    end
    else
    if( promptId == PAGE2 )
    begin
      for(i=0; i<txPage2.len(); i++)
        str[i]=txPage2[i];
    end
    else
    if( promptId == PAGE3 )
    begin
      for(i=0; i<txPage3.len(); i++)
        str[i]=txPage3[i];
    end

    return str;
endfunction

endmodule
2

Since you are accessing fixed-size chunks you can use your packed array

bit [0:87] BIT_ARRAY = "Hello world";

and part-select the individual bytes using the +: (or -:) operators.

For example,

BIT_ARRAY [0 +: 8]

access the character “H”.

3

In reply to SparkyNZ:

You can use the streaming operator to simplify your existing code

 if( promptId == PAGE1 )
    str = {>>{txpage1}};