Defining macro based on parameter value

SystemVerilog
,
1

I am trying to define a macro using parameter value, something like this:


if (RESET_POLARITY == 1) `define RESET_EDGE posedge rst
else                     `define RESET_EDGE negedge rst

So that in the always block sensitivity list I can do this:

always @(posedge clk or `RESET_EDGE) begin
   if (rst == RESET_POLARITY) begin
      // reset logic
   end
   else begin
      // clocked logic
   end
end

However the macro definition throws compile error. Is there anyway to implement my intention in SV?

2

In reply to Mitu Raj:

Macros get defined and expanded before any SystemVerilog code gets parsed. So you are effectively defining two macros with the same name.

You could use an xor operator to get the behavior you are looking for

always @(posedge clk or negedge rst^RESET_POLARITY) begin
   if (rst^RESET_POLARITY) begin
      // reset logic
   end
   else begin
      // clocked logic
   end
end

You can also use a macro or the let construct

`define RESET rst^RESET_POLARITY
always @(posedge clk or negedge `RESET) begin
   if (`RESET) begin
      // reset logic
   end
   else begin
      // clocked logic
   end
end

let RESET = rst^RESET_POLARITY;
always @(posedge clk or negedge RESET) begin
   if (RESET) begin
      // reset logic
   end
   else begin
      // clocked logic
   end
end
3

In reply to dave_59:

Thanks Dave, I have used the second method. However the if condition has to be inverted since it’s being triggered on negedge.

if (!`RESET)