Defining dynamic bins [ ] for ignore_bins , Legal?

SystemVerilog
, , ,
1

I am trying following code ::


   bit [3:0]  adr1 ;

   covergroup  user_cvr_grp ;     
      ac : coverpoint adr1      
      { 
        ignore_bins  igvalues0[]  =  { 4 , 5 }  ;   
        ignore_bins  igvalues1[]  =  { [6:$] }  ;   
      }
  endgroup

I expected :
02 dynamic / multiple bins would be created for igvalues0
10 dynamic / multiple bins would be created for igvalues1
04 automatic bins would be created for coverpoint ac

However I observe a warning message ::
" Array syntax ‘[]’ has no effect on ignore_bins and illegal_bins. Multi-stateness is ignored. Capturing multi-bin data in a single bin."

And I observe 1 dynamic bin is created each for igvalues0 and igvalues1.

Are dynamic / multiple bins legal for ignore_bins ? Similarly can they be defined for illegal_bins and wildcard bins ?

2

In reply to hisingh:

Your code is legal. However, there is no requirement to create an ignored bin or set of bins and count hits since they will not be part of the coverage computation. Doing so would be useful for debugging only.