I came across some issue to understand about +define+macro vs define Macro in SV.
When passing macro define from compile option like +define+macro always takes effect even if it is put at the end of the file.
But it is different when a SV macro puts in the SV file.
I am confused on that. Can someone give some clue how tool process +define+macro differently from the SV macro in SV file?
module tb;
`ifdef TOMMA
string name = "tomma";
`else
string name = "matthewma";
`endif
//`define US
`ifdef US
string cn = "USA";
`else
string cn = "ASU";
`endif
initial begin
$display("name:%s",name); //why name's value even if +define+TOMMA after tb.sv, how tool handle SV macro in this case? Does macro define order not matter?
$display("cn:%s",cn); //expected, as US define after cn declaration, so cn = "ASU"
end
`define US
endmodule
This borders on a tool specific issue, but generally tool command line options like +define get applied before parsing any code. Otherwise all compiler directives like `define get processed in the order they appear in your source code.
`define is a compiler directive which is described in section 22.5.1 of the SystemVerilog LRM. Section 22.2 of LRM describes how compiler directives only extend from the point where it is processed.
The compile argument +define+ is a tool specific argument with behavior dependent on the tool implementation. In most cases, it is equivalent to adding a `define to the beginning of every file being compiled. You will need to refer to your tool documentation for additional information.
You should also be aware of how tools handle compilation units and how compiler directives may or may not carry over from one file to another.