Define vs. parameter - difference

SystemVerilog
1

Hi,

What are the differences between using define and parameter?
Aside of the fact that the parameter is like a const and `define is compiler directive.
Is there any difference from runtime point of view?


`define NUM_OF_PROFILES   1024
parameter MAX_NUM_OF_PROFILES           = 2048;

Thanks in advance!

2

In reply to Michael54:

Macros are basically text substitutions, this will be expanded during compile time, Parameters on the other hand are just constants that are resolved at elaboration time.

With macros you can do things like:

define MAX(p,q) (p)>(q)?(p):(q) ... #MAX(delay1, delay2);

HTH,

-R

3

In reply to rgarcia07:

Macros ARE just text substitutions. They do appear to have overlapping functionality, so in Michael54’s example, there is no difference in runtime execution.

Macros, parameters, and const variables all have features available in some but not others.

const variables get initialized once at the beginning of their lifetime. So if you have a const variable inside a procedural for-loop, that variable could get initialized at every iteration during runtime. Because const variables get initialized at runtime, you can't use them where constant expressions are required by the compiler, like the size in a declaration.

Parameter values can be overridden on a module instance by instance basis. And some tools even allow to override parameter values when you invoke simulation. You can’t do either using a macro.

4

In reply to dave_59:

Hi Dave, can you help me with this ?


module top_driver #(parameter START_LANE = 0)

`define LANE_ID(lane_no)\
lane_drv u_lane``lane_no``_drv ()

`LANE_ID(0 + START_LANE) // 0 + parameter set for START_LANE when top_driver instantiated 
`LANE_ID(1 + START_LANE)
`LANE_ID(2 + START_LANE)
`LANE_ID(3 + START_LANE)
endmodule

it is giving me compile error as parameter and `define can not work together

error - u_lane0 + START_LANE_drv // creating instance like this

what I want is, whatever LANE number I give when top_driver is instantiated lane_driver should start from that

example if START_LANE is 0, my lane driver should look like this,
u_lane0_drv()
u_lane1_drv()
u_lane2_drv()
u_lane3_drv()

and if START_LANE is 4, my lane driver should be,
u_lane4_drv()
u_lane5_drv()
u_lane6_drv()
u_lane7_drv()

5

In reply to J_M:

Macros ARE just text substitutions. They have no knowledge of SystemVerilog syntax and just pass the argument text through.

What you might want to use is a generate-for loop

module top_driver #(parameter START_LANE = 0)
 
for (genvar i = START_LANE; i<START_LANE+4;i++ begin : lane
     lane_drv u ()

endmodule

This creates instance names lane[0].u, lane[1].u, lane[2].u, and lane[3].u. See section 27.4 Loop generate constructs in the IEEE 1800-2017 SystemVerilog LRM.