Hello Forum,
Could you please help me to know how to know the default value of the signal using
assertions.
Thanks and Regards
Sunil SHarma.
In reply to sunils:
Could you please help me to know how to know the default value of the signal using
assertions.
An assertion is used to verify that a property of a design is true; it is not a predictor.
Thus, you can us assertions, like the following examples, to verify that a signal went into your expected default value.
logic x, y;
bit clk, reset_n; // active low
ap_reset: assert property($rose(reset_n) |-> x=1'b0);
@(posedge clk) begin
....
a_immy: assert (y==1'b1);
end
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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