Default skew of clocking block input signals and output signals + scheduling semantics region of these signals

SystemVerilog
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  1. If we don’t mention skews for a clocking block definition , are the default skews #1 for input and #0 for output?
  2. for the clocking input which region from the SV scheduling semantics(event regions) are we sampling this value from(as we are sampling a previous value before this clock edge)
    3)For the clocking output, In which event region are we going to schedule the drive?
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In reply to hsam:

The last paragraph of section 14.3 Clocking block declaration in the IEEE 1800-2017 SystemVerilog LRM should answer your first question, and the next section 14.4 Input and output skews should answer your other questions.