Default return type in SystemVerilog

Is void the default return type in Systemverilog? I came across a function(shown below) that had no return type mentioned but was using an empty return. Does this mean that test() is of type void since it has no return type? And is it legal to use an empty return(as shown below) in systemverilog?

virtual function test();
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if(condition)
   return;
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endfunction: test

In reply to vikrant_sharma:

For backward compatibility with Verilog, the default return type of a function is a 1-bit logic. The LRM currently says

When the return statement is used, nonvoid functions shall specify an expression with the return.

Then the inverse rule is: a return statement without an expression inside a nonvoid function is illegal.